Peripheral Component Interconnect Express, PCIe 2.0 specifies 5.0 Gigbit/s symbol rate per lane. Multiple lanes can be used to fabricate larger port bandwidths. For example, a x4 port would have an aggregate symbol rate of 20B, and a bit rate of 16F, if 8b10b coding is used. A x8 port would have an aggregate symbol rate of 40G, and a bit rate of 32G. There are other serial interconnect protocols, for example serial rapid IO that have similar properties. This disclosure will focus on PCIe, but is not limited to that protocol.
In certain serial protocols (PCIe, SRIO, for example), a port can bifurcate. What this means is that a x8 port may split into two x4 ports. An example of a typical implementation of how this is achieved is shown in FIG. 1. The x4 port 10 includes a x4 media access controller (MAC) 12, a first x64 RAM 14, a x1 MAC 16 and a second x64 RAM 18 coupled to an internal switch fabric (ISF) 20. This example is SRIO where the x4 port can bifurcate into 2x1. The port 10 shown in FIG. 1 is configured to run as 1x4. Note that the ISF (Internal Switch Fabric) has more ports than are shown.
Referring to FIG. 2, the bifurcate port of FIG. 1 is shown configured for 2x1 operation. The architecture of FIGS. 1 and 2 is simple conceptually, and is the typical way of attaching bifurcated ports to an ISF. But it wastes buffers in the 1x4 mode, and doubles the ISF bandwidth. The port speed is 10 G in the 1x4 mode, and the ISF port bandwidth consumed is 20 G. Both of these items add area and thus cost to the implementation.